1. Field of Invention
The present invention relates to a method for checking a design rule of layout. More particularly, the present invention relates to a method for inspecting the design rule of layout according to the characteristics of layers in the layout.
2. Description of Related Art
In the design and development of semiconductor chips, the design rule check (DRC) is a program for checking whether the semiconductor integrated circuit follows the topological layout rules (TLR) or not. The topological layout rules have particular rules depending on different process techniques and instrument limitation between wafer factories.
Referring to FIG. 1, it is a conventional flow chart of a method for inspecting whether semiconductor integrated circuits meet the design rules or not, which comprises the following steps.
First, as shown in step 110, a layout comprising a plurality of layers and being in global distribution system (GDS) format is provided. Then, as shown in step 120, the corresponding topological layout rules are determined in manual manner according to different process techniques, conditions of wafer factories, and characters in chips. Next, as shown in step 130, according to the topological layout rules determined in step 120, a corresponding command file is fetched from a prepared command file database 140. In step 150, the layout is inspected and checked by using the design rule check tool according to this command file. Any design error found in the process is shown in the check result 160.
As for the conventional design rule check flow, engineers must design different command files for different process techniques. As current design rule check tools cannot provide information about whether a certain layer exists in the layout or not, it is necessary to manually search the maximum number of layers and select the corresponding command file according to different wafer sizes. No matter whether a suitable program is selected from the design command file database or from the command file database according to the characters in chips so as to perform the design rule check, a large amount of time will be spent which further negatively affects the whole flow of IC design.